Unlike modern complex CPU architectures, the 6502 relies on an ultra-minimal set of registers:
Zero-Page Optimization ($00–$FF): The first 256 bytes in RAM require only an 8-bit address operand, executing a full clock cycle faster per instruction.
Changing the screen border color synchronized to the electron beam of the CRT monitor:
* = $c000 ; Origin in RAM (SYS 49152)
sei ; Disable maskable interrupts
lda #$7f
sta $dc0d ; Disable CIA1 timer interrupts
lda #$01
sta $d01a ; Enable VIC-II raster interrupt signals
lda #100 ; Target rasterline (Line 100)
sta $d012
lda $d011
and #$7f ; Clear 8th bit of rasterline
sta $d011
lda #<irq_routine ; Low-byte of handler
sta $0314 ; Hook into KERNAL IRQ vector
lda #>irq_routine ; High-byte of handler
sta $0315
cli ; Re-enable interrupts
rts ; Return to BASIC
irq_routine:
inc $d020 ; Flash border color register (Rasterbar effect)
dec $d020 ; Restore border color
asl $d019 ; Acknowledge VIC-II interrupt
jmp $ea31 ; Exit via default KERNAL IRQ handler